1. Field of the Invention
The present invention generally relates to semiconductor devices and method for manufacturing the same, and more particularly to stackable structures for semiconductor integrated circuit packages and method for manufacturing the packages.
2. Description of the Related Arts
In general, semiconductor dies or chips are individually packaged for use in plastic or ceramic packages. A plurality of outer leads protruding from the package body are soldered on a supporting substrate such as a printed circuit board, or inserted into a socket. These packages, especially the packages inserted into the socket, have a large mounting area occupied on the printed circuit board.
The printed circuit board is being developed toward a smaller size and a higher density, and thereby requires a higher-density packaging technique. Therefore, a multichip module (MCM) or multichip package (MCP) capable of supporting several chips on a single package, has been developed.
The MCM or the MCP decreases the time delay between the chips, the electrical noise, and the crosstalk. Further, the MCM can employ much larger-sized chips, increase the number of I/O leads, and improve package mounting density to the substrate.
However, the above-described MCM has several drawbacks. Bare silicon chips for MCM cannot be tested before the chips are packaged. And, any one chip that is defective causes the entire module to fail when tested. Thus, the MCM is faced with poor yields and little chance of rework. In addition, MCM technology does not permit burn-in of bare silicon chips; burn-in must be done at the module level.
A stacked package has been introduced as an alternative to the MCM. The stacked package not only reduces its overall size, but also allows for chip-level tests or burn-in before packaging. These three-dimensional stacked packages are disclosed in, for example, U.S. Pat. Nos. 5,138,438, 5,172,303, 5,198,888, and 4,763,188. Since the stacked package can improve the mounting density to the substrate and connecting density between the packages, it is applicable in a super computer and a large-scale cache memory.
However, since individual packages used in the stacking structure are much thicker than the individual chips, the overall thickness of the stacked package increases considerably. It is therefore desirable to reduce the thickness of the individual packages and thereby realize thinner stacked packages.
Moreover, in the prior art stacked package structures it was necessary to deform or bend the package leads in order to interconnect upper and lower packages, and this reduced the yield of the stacked package. For example, the outer leads of an upper package are typically connected to the outer leads of a lower package, or each of the outer leads of a plurality of packages are provided with a hole and the packages are stacked on a frame which includes a plurality of pins. The packages are stacked by maneuvering the packages so that the leads are aligned with the plurality of pins.